VHDLで符号拡張がうまくいかない

VHDLの下記のソースコードで、コンパイル中に次のようなエラー文が出ました。「Error (10395): VHDL Conditional Signal Assignment error at mips_datapath.vhdl(150): conditional waveforms must have same number of elements」
しかし、該当する150行目( signimm <= X"0000" & immaddr when immaddr(15) = '0' else X"FFFF" & signimm;)を見てもどこがおかしいのかよく分かりませんでした。このエラーの原因と対処方法が分かりましたら教えて下さい。該当のソースコードは以下の通りです。

vhdl
1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.std_logic_unsigned.all;
4
5entity mips_datapath is
6  port (
7    clk, rst                 : in  std_logic;
8    rd1sel, branch, jump     : in  std_logic;
9    regwrite, regdst, r31Set : in  std_logic;
10    alusrc                   : in  std_logic;
11    memwrite                 : in  std_logic;
12    memtoreg, pc4toreg       : in  std_logic;
13    alucontrol               : in  std_logic_vector(2 downto 0);
14    instr                    : out std_logic_vector(31 downto 0);  -- to Controller
15    pc, aluout, writedata    : out std_logic_vector(31 downto 0));  -- to Data Memory
16	 
17end mips_datapath;
18
19architecture structure of mips_datapath is
20
21  component imem
22    port (
23      addr : in  std_logic_vector(31 downto 0);
24      rd   : out std_logic_vector(31 downto 0));
25  end component;
26
27  component alu
28    port (
29      srcA, srcB : in  std_logic_vector(31 downto 0);
30      alucontrol : in  std_logic_vector(2 downto 0);
31      aluout     : out std_logic_vector(31 downto 0);
32      zero       : out std_logic);
33  end component;
34
35  component regfile
36    port (
37      clk           : in  std_logic;
38      we3           : in  std_logic;
39      ra1, ra2, wa3 : in  std_logic_vector(4 downto 0);
40      wd3           : in  std_logic_vector(31 downto 0);
41      rd1, rd2      : out std_logic_vector(31 downto 0));
42  end component;
43
44  component dmem
45    port (
46      clk      : in  std_logic;
47      we       : in  std_logic;
48      addr, wd : in  std_logic_vector(31 downto 0);
49      rd    : out std_logic_vector(31 downto 0));
50  end component;
51
52  component signext
53    port (
54      a        : in  std_logic_vector(15 downto 0);
55      y        : out std_logic_vector(31 downto 0));
56  end component;
57
58   signal PCreg, pc_next	: std_logic_vector(31 downto 0);
59	signal pc4, pcjump, pcbranch : std_logic_vector(31 downto 0);
60
61	signal signimm : std_logic_vector(31 downto 0);
62
63	signal inst : std_logic_vector(31 downto 0);-- 命令メモリからの出力
64
65	signal srcA, srcB : std_logic_vector(31 downto 0);-- ALUへの入力
66	signal rs : std_logic_vector(4 downto 0);
67	signal rt : std_logic_vector(4 downto 0);
68	signal rd : std_logic_vector(4 downto 0);
69	signal wa3 : std_logic_vector(4 downto 0);
70	signal rd1, rd2 : std_logic_vector(31 downto 0);
71	signal immaddr : std_logic_vector(15 downto 0);
72	signal WriteAddr : std_logic_vector (4 downto 0); -- 書き込みアドレス
73   signal WriteData0 : std_logic_vector (31 downto 0); -- 書き込みデータ
74	signal ALUout0 : std_logic_vector (31 downto 0); -- からの出力ALU
75begin
76
77  -----------------------------------------------------------------------------
78  -- プログラムカウンタ
79  pc <= PCreg;
80
81  process (clk, rst)
82  begin
83    if rst = '0' then
84      PCreg <= X"00000000";
85    elsif clk'event and clk = '1' then
86      PCreg <= pc_next;
87    end if;
88  end process;
89
90  -- 次のPCのアドレスを計算する
91  process (jump, branch,  rd1sel, pcjump, pcbranch, srcA, pc4)
92  begin
93    if jump = '1' then
94      pc_next <= pcjump;
95    elsif branch = '1' then
96      pc_next <= pcbranch;
97    elsif rd1sel = '1' then
98      pc_next <= srcA;
99    else
100      pc_next <= pc4;
101    end if;
102  end process;
103  pc4      <= PCreg + 4;
104  pcjump   <= pc4(31 downto 28) & inst(25 downto 0) & "00";
105  pcbranch <= (signimm(29 downto 0) & "00") + pc4;
106  -----------------------------------------------------------------------------
107
108  -----------------------------------------------------------------------------
109  -- Instruction Fetch
110  IMEM0 : imem port map (
111    addr  => PCreg,
112    rd    => inst);
113
114  -----------------------------------------------------------------------------
115  -- Instruction Decode
116  -- レジスタファイル
117  -- Instruction Memoryの出力信号をinstructionとする
118  instr   <= inst;                      -- 出力
119  rs      <= inst(25 downto 21);
120  rt      <= inst(20 downto 16);
121  rd      <= inst(15 downto 11);
122  immaddr <= inst(15 downto 0);
123  
124  RF : regfile port map (
125    clk => clk,
126		we3 => regwrite,
127		ra1 => rs,
128		ra2 => rt,
129		wa3 => rd,
130		wd3 => inst);
131
132  process (rt, rd, regdst, r31set)
133  begin
134    if r31Set = '1' then
135      wa3 <= "11111";
136    elsif regdst = '1' then
137      wa3 <= rd;
138    else
139      wa3 <= rt;
140    end if;
141  end process;
142
143  -----------------------------------------------------------------------------
144  -- Execution
145
146  -- ALUの接続
147  -- 符号拡張するところに注意
148	
149  signimm <=
150  X"0000" & immaddr when immaddr(15) = '0' else X"FFFF" & signimm;
151
152	ALU0 : alu port map (
153		srcA => srcA ,
154		srcB => signimm ,
155		alucontrol => alucontrol ,
156		aluout => ALUout0);
157  -----------------------------------------------------------------------------
158
159  -----------------------------------------------------------------------------
160  -- Memory
161  WriteData <= Writedata0 ;
162  -- Data Memoryまわりの接続
163  MEM0 : dmem port map (
164    clk  => clk,
165    we   => MemWrite,
166    addr => ALUout0,
167    wd   => rd2,
168    rd   => writedata);
169
170  -----------------------------------------------------------------------------
171  
172end structure;
173