回答編集履歴
1
修正
test
CHANGED
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@@ -6,14 +6,14 @@
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6
6
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output reg [7:0] dest
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7
7
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);
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8
8
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9
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-
reg [7:0] j; // logic -> reg
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10
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-
logic [7:0]
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9
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+
logic [7:0] j;
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10
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+
logic [7:0] src[7:0]; // ここを変えた
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11
11
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12
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-
always @(posedge clock) begin
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12
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+
always_ff @(posedge clock) begin
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13
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j <= j + 1;
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14
14
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end
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15
15
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16
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-
always @(posedge clock) begin
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16
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+
always_ff @(posedge clock) begin
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dest <= src[j][7:0];
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18
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end
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19
19
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