回答編集履歴
4
修正
test
CHANGED
|
@@ -55,7 +55,7 @@
|
|
|
55
55
|
|
|
56
56
|
// 略
|
|
57
57
|
/*パターン表示回路を接続*/
|
|
58
|
-
counter
|
|
58
|
+
counter #(.S(10))pattern(
|
|
59
59
|
.CLK(CLK),
|
|
60
60
|
.RES(RES),
|
|
61
61
|
.LED(LED)
|
3
追加
test
CHANGED
|
@@ -30,3 +30,35 @@
|
|
|
30
30
|
end
|
|
31
31
|
// 省略
|
|
32
32
|
```
|
|
33
|
+
|
|
34
|
+
|
|
35
|
+
---
|
|
36
|
+
|
|
37
|
+
|
|
38
|
+
```verilog
|
|
39
|
+
`timescale 1ns / 1ps
|
|
40
|
+
|
|
41
|
+
module counter #(parameter S=99999999)(
|
|
42
|
+
// 略
|
|
43
|
+
always @(posedge CLK or negedge RES) begin
|
|
44
|
+
if (RES == 1'b0)
|
|
45
|
+
scale <= 27'd0;
|
|
46
|
+
else if (scale == S) begin //scaleが溜まったらscaleをリセット
|
|
47
|
+
// 略
|
|
48
|
+
```
|
|
49
|
+
|
|
50
|
+
|
|
51
|
+
```verilog
|
|
52
|
+
`timescale 1ns / 1ps
|
|
53
|
+
|
|
54
|
+
module counter_test;
|
|
55
|
+
|
|
56
|
+
// 略
|
|
57
|
+
/*パターン表示回路を接続*/
|
|
58
|
+
counter pattern#(.S(10))(
|
|
59
|
+
.CLK(CLK),
|
|
60
|
+
.RES(RES),
|
|
61
|
+
.LED(LED)
|
|
62
|
+
);
|
|
63
|
+
// 略
|
|
64
|
+
```
|
2
追記
test
CHANGED
|
@@ -11,6 +11,9 @@
|
|
|
11
11
|
|
|
12
12
|
|
|
13
13
|
---
|
|
14
|
+
|
|
15
|
+
> LED[3:0]の部分が”X”となっています。
|
|
16
|
+
|
|
14
17
|
```verilog
|
|
15
18
|
`timescale 1ns / 1ps
|
|
16
19
|
|
1
コード追加
test
CHANGED
|
@@ -8,3 +8,22 @@
|
|
|
8
8
|
wire [23:0] scale = pattern.scale;
|
|
9
9
|
```
|
|
10
10
|
としましょう
|
|
11
|
+
|
|
12
|
+
|
|
13
|
+
---
|
|
14
|
+
```verilog
|
|
15
|
+
`timescale 1ns / 1ps
|
|
16
|
+
|
|
17
|
+
module counter (
|
|
18
|
+
input wire CLK, RES,
|
|
19
|
+
output reg [3:0]LED);
|
|
20
|
+
|
|
21
|
+
reg [26:0] scale;
|
|
22
|
+
|
|
23
|
+
always @(posedge CLK or negedge RES) begin
|
|
24
|
+
if (RES == 1'b0) begin
|
|
25
|
+
scale <= 27'd0;
|
|
26
|
+
LED <= 4'b0; // リセットを追加
|
|
27
|
+
end
|
|
28
|
+
// 省略
|
|
29
|
+
```
|