[DRC LUTUP-1]Combination Loop Alertが解消できない

Question

前提・実現したいこと

XilinxのVivadoと、DigilentのBASYS3を用いて、Microchip社のDAC,MCP4911を駆動するためのコードを書いています。

実現したい出力は、データシートの25ページ目、Figure 5-2の波形の、¬CS、SCK、SDIです。

Simulation上では想定通りの動作を確認しましたが、Generate Bitstreamの段階でCombination Loop Alertによりエラーが出てしまいます。

発生している問題・エラーメッセージ

[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is c_SCK[0]. Please evaluate your design. The cells in the loop are: SCK_reg_i_5.

[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is c_SCK[1]. Please evaluate your design. The cells in the loop are: SCK_reg_i_4.

[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is c_SCK[2]. Please evaluate your design. The cells in the loop are: SCK_reg_i_3.

該当のソースコード

`timescale 1ns / 1ps

module MCP4911_01a_main(clk,CSb,SCK,SDI);
    input   clk;
    output  reg CSb = 1;
    output  reg SCK = 0;
    output  reg SDI = 0;   
    
    reg bit15 = 0;
    //0:Write to DAC register
    //1:Ignore
    
    reg BUF     = 0;
    //0:Unbuffered
    //1:Buffered
    
    reg GAb     = 1;
    //0:2x Vout
    //1:1x Vout
    
    reg SHDNb   = 1;
    //0:Shutdown the device
    //1:Active
    
    reg [9:0] D = 257;              //data
     
    reg [1:0] state = 0;
    
    reg [7:0] count = 0;

    reg [2:0] c_SCK = 0;             //count to generate SCK/~SCK
    reg [3:0] dig = 15;              //16 digits
    reg [7:0] dig_total = 47;        //16 digits times 3 state equals 48 bits
    wire [15:0] buff_SDI = {bit15,BUF,GAb,SHDNb,D,2'b00};
    wire [15:0] buff_SDI_start = 0;         
    wire [15:0] buff_SDI_end = 0;           
    reg f_gen_SCK = 0;               //flag to generate SCK and ~SCK
    
    always @(clk) begin
        
        c_SCK <= c_SCK + 1;
        
        if (c_SCK == 1) begin
            case(state)
                0:
                SDI <= buff_SDI_start[dig];
                1:
                SDI <= buff_SDI[dig];
                2:
                SDI <= buff_SDI_end[dig];
            endcase
        end else if (c_SCK == 7) begin
            dig <= dig - 1;
            dig_total <= dig_total - 1;
            if (dig_total == 0) begin
                dig_total <= 47;
            end
            if (dig == 0) begin                
                state <= state + 1;
                if (state == 2) begin
                    state <= 0;
                end
            end
        end
        
        if (f_gen_SCK) begin
            case (c_SCK)
                7: SCK <= 0;
                3: SCK <= 1;
            endcase
        end
        
        case(dig_total)
            32:     CSb <= 0;
            31:     f_gen_SCK <= 1;
            15: begin
                    f_gen_SCK <= 0;
                    CSb <= 1;
            end
        endcase        
    end
    
endmodule

試したこと

代入の回数を減らすなどして、配線の干渉が起きにくくなるように工夫したが、エラーメッセージは変化しなかった

補足情報（FW/ツールのバージョンなど）

Simuration結果

FPGA: xc7a35tcpg236-1
ボード: BASYS 3
使用したいDAC: MCP4911
Vivado: v2019.1 (64-bit)

Answer 1

always 文のセンシビリティリストが間違っていはいませんか？

always @(posedge clk) begin
// 以下略
end

の間違いではないでしょうか？
(clk の前の posedge 抜け)

Comments

[ack05]

返信が遅れてしまい申し訳ございませんでした．
条件にposedgeをつけたところエラーが解消されました．ありがとうございます．

ただ，解決した原理はまだ理解に至っていません．
always @(clk) beginと，always @(posedge clk) beginでは単に動作速度が倍になるかそうでないかの違いであると思っています．なぜこの違いだけでCombinatorial Loopが生じるのでしょうか．
もしご存知でしたら教えていただけないでしょうか．

[taichi730]

両エッジ駆動になってて、FFを推定できなかったからとか？
記述をどう解釈するかは処理系次第ってことです。