質問編集履歴
1
プログラム変更
test
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File without changes
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test
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@@ -50,7 +50,33 @@
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end
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endmodule
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```
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変更後
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54
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```Verilog
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55
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module counter (
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56
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input wire CLK, RES,
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output reg [3:0]COUNT);
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reg [23:0] scale;
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always @(posedge CLK or negedge RES) begin
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if (RES == 1'b0)
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scale <= 24'h0;
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else if (scale == 24'd9999999)
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scale <=24'd0;
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else
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scale <=scale + 24'd1;
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end
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assign wire EN = scale == 24'd9999999;
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always @(posedge CLK or negedge RES) begin
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if (RES == 1'b0)
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COUNT <= 4'd0;
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else if(EN == 1'b1)
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COUNT <= COUNT + 4'd1;
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end
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endmodule
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```
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### 試したこと
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55
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ここに問題に対して試したことを記載してください。
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