Vivadoによるカウンタ作成

Question

実現したいこと

• btn0をおすとカウンタのスタートとストップができる
• sw0が0のときはカウントアップ、sw1が1のときはカウントダウン
• sw1が0のときは16進、sw1が1のときは10進のカウンタ

前提

発生している問題・エラーメッセージ

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 8 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: btn0, and sw1.

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 8 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: btn0, and sw1.

該当のソースコード

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/07/18 14:02:29
// Design Name: 
// Module Name: task22_x_202211666
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module task22_x_202211666(
    input clk,
    input btn0,
    input sw0, //0でカウントアップ
    input sw1, //1で10進
    output [3:0]ld
    );
    
reg [3:0]hexcnt;
reg [31:0]scnt;
reg r0,r1;
wire pulse;
always@(posedge clk)begin
    r0 <= btn0;
    r1 <= r0;
end


parameter SMAX = 125000000-1;

initial begin
    hexcnt <= 0;
    scnt <= 0;
end
assign pulse = r1 & ~r0;

reg en;
always@(posedge clk)begin
    if(pulse == 1)begin
        en <= ~en;
    end
end


always@(posedge clk)begin
    if(scnt < SMAX)begin
        scnt <= scnt + 1;
    end else begin
        scnt <= 0;
    end
end

always@(posedge clk)
    if(scnt == SMAX)begin
    if(en == 1)begin
        if(sw1 == 1)begin //10進
            if(sw0 == 0)begin //up
                if(hexcnt == 9)begin
                    hexcnt <= 0;
                end else begin
                    hexcnt <= hexcnt + 1;
                end
             end else begin
                hexcnt <= hexcnt - 1;
            end
        end else begin //16進
            if(sw0 == 0)begin //up
                hexcnt <= hexcnt + 1;
            end else begin
                hexcnt <= hexcnt - 1;
            end
        end
    end
    end
    
assign ld = hexcnt;

endmodule

set property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {clk}];
create_clock -period 8.000 -name sys_clk_pin -waveform {0 4} -add [get_ports {clk}];

set property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {ld[0]}];
set property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {ld[1]}];
set property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {ld[2]}];
set property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {ld[3]}];

set property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {btn0}];

set property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {sw0}];
set property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {sw1}];

試したこと

xdcファイルに原因がありそうなので、タイプミスを確認したがタイプミスはなかった。chatGPTにもかけてみたが、正しそうだった。

補足情報（FW/ツールのバージョンなど）

vivado 2023.1
windows11

Answer 1

set propetyではなくset_propertyでした。