VuMUL_bi_1wire_test& operator= (const VuMUL_bi_1wire_test&); ///< Copying not allowed
VuMUL_bi_1wire_test(const VuMUL_bi_1wire_test&); ///< Copying not allowed
と書かれている部分の意味が分かりません。
operatorに関して調べましたが、上の動作がどうなっているのかいまいち理解できませんでした。
一つ目はインスタンスのコピー操作を追加でしょうか。
二個目に関しては理解できません。
VuMUL_bi_1wire_testというClassのprivate部分に書かれています。
回答の程よろしくお願いいたします。
C++
1// Verilated -*- C++ -*- 2// DESCRIPTION: Verilator output: Primary design header 3// 4// This header should be included by all source files instantiating the design. 5// The class here is then constructed to instantiate the design. 6// See the Verilator manual for examples. 7 8#ifndef _VuMUL_bi_1wire_test_H_ 9#define _VuMUL_bi_1wire_test_H_ 10 11#include "verilated.h" 12 13class VuMUL_bi_1wire_test__Syms; 14class VerilatedVcd; 15 16//---------- 17 18VL_MODULE(VuMUL_bi_1wire_test) { 19 public: 20 21 // PORTS 22 // The application code writes and reads these signals to 23 // propagate new values into/out from the Verilated model. 24 VL_IN8(clk,0,0); 25 VL_IN8(rst_n,0,0); 26 VL_IN8(iA_trigger,0,0); 27 VL_IN8(iB_value,7,0); 28 VL_IN8(iA_value,7,0); 29 VL_IN8(loadA,0,0); 30 VL_IN8(loadB,0,0); 31 VL_OUT8(cntNum_iA,7,0); 32 VL_OUT8(cnt,7,0); 33 VL_OUT8(oC_sum,7,0); 34 35 // LOCAL SIGNALS 36 // Internals; generally not touched by application code 37 VL_SIG8(uMUL_bi_1wire_test__DOT__iA,0,0); 38 VL_SIG8(uMUL_bi_1wire_test__DOT__iA_buf,7,0); 39 VL_SIG8(uMUL_bi_1wire_test__DOT__iA_sobolSeq,7,0); 40 VL_SIG8(uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT__vecIdx,2,0); 41 VL_SIG8(uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT__u_cntWithEn__DOT__cnt,7,0); 42 VL_SIG8(uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT__u_LSZ__DOT__inacc,7,0); 43 VL_SIG8(uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT__u_LSZ__DOT__outoh,7,0); 44 VL_SIG8(uMUL_bi_1wire_test__DOT__u_cntWithEn_A__DOT__cnt,7,0); 45 VL_SIG8(uMUL_bi_1wire_test__DOT__uMUL_bi_1wire__DOT__iB_buf,7,0); 46 VL_SIG8(uMUL_bi_1wire_test__DOT__uMUL_bi_1wire__DOT__counter_switch__DOT__cnt,7,0); 47 VL_SIG8(uMUL_bi_1wire_test__DOT__uMUL_bi_1wire__DOT__counter_switch__DOT__sum,7,0); 48 VL_SIG8(uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT__dirVec[8],7,0); 49 50 // LOCAL VARIABLES 51 // Internals; generally not touched by application code 52 static VL_ST_SIG8(__Vtable1_uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT__vecIdx[256],2,0); 53 VL_SIG8(__Vtableidx1,7,0); 54 VL_SIG8(__Vclklast__TOP__clk,0,0); 55 VL_SIG8(__Vclklast__TOP__rst_n,0,0); 56 VL_SIG8(__Vchglast__TOP__uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT__u_LSZ__DOT__inacc,7,0); 57 VL_SIG(__Vm_traceActivity,31,0); 58 VL_SIG8(uMUL_bi_1wire_test__DOT__U_SobolRNGDim1__DOT____Vcellinp__u_SobolRNG__dirVec[8],7,0); 59 60 // INTERNAL VARIABLES 61 // Internals; generally not touched by application code 62 VuMUL_bi_1wire_test__Syms* __VlSymsp; // Symbol table 63 64 // PARAMETERS 65 // Parameters marked /*verilator public*/ for use by application code 66 67 // CONSTRUCTORS 68 private: 69 VuMUL_bi_1wire_test& operator= (const VuMUL_bi_1wire_test&); ///< Copying not allowed 70 VuMUL_bi_1wire_test(const VuMUL_bi_1wire_test&); ///< Copying not allowed 71 public: 72 /// Construct the model; called by application code 73 /// The special name may be used to make a wrapper with a 74 /// single model invisible WRT DPI scope names. 75 VuMUL_bi_1wire_test(const char* name="TOP"); 76 /// Destroy the model; called (often implicitly) by application code 77 ~VuMUL_bi_1wire_test(); 78 /// Trace signals in the model; called by application code 79 void trace (VerilatedVcdC* tfp, int levels, int options=0); 80 81 // API METHODS 82 /// Evaluate the model. Application must call when inputs change. 83 void eval(); 84 /// Simulation complete, run final blocks. Application must call on completion. 85 void final(); 86 87 // INTERNAL METHODS 88 private: 89 static void _eval_initial_loop(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 90 public: 91 void __Vconfigure(VuMUL_bi_1wire_test__Syms* symsp, bool first); 92 private: 93 static QData _change_request(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 94 public: 95 static void _combo__TOP__3(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 96 private: 97 void _ctor_var_reset(); 98 public: 99 static void _eval(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 100 private: 101#ifdef VL_DEBUG 102 void _eval_debug_assertions(); 103#endif // VL_DEBUG 104 public: 105 static void _eval_initial(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 106 static void _eval_settle(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 107 static void _sequent__TOP__2(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 108 static void _settle__TOP__1(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp); 109 static void traceChgThis(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 110 static void traceChgThis__2(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 111 static void traceChgThis__3(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 112 static void traceChgThis__4(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 113 static void traceChgThis__5(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 114 static void traceChgThis__6(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 115 static void traceFullThis(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 116 static void traceFullThis__1(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 117 static void traceInitThis(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 118 static void traceInitThis__1(VuMUL_bi_1wire_test__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); 119 static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code); 120 static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code); 121 static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code); 122} VL_ATTR_ALIGNED(128); 123 124#endif // guard
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2021/04/30 18:53