VHDLで４桁BCD回路のシミュレーションを実行したときにエラーが発生する

VHDLで4桁のBCD加算器を実装しています。プロジェクトのソースコードは以下の通りです。コンパイルには成功しましたが、RTLシミュレーションを行ったところ、以下のようなエラー文が表示されました。

Fatal: (vsim-3817) Port "x" of entity "bcdadder_4bit" is not in the component being instantiated.
#    Time: 0 ps  Iteration: 0  Instance: /test_bcdfa4bit/BCDFA4BIT0 File: C:/Users/(ユーザー名)/VDHL/bcdadder_4bit.vhd Line: 7

画像も下に添付します。

エラー文は"x"がインスタンス化なされていないという意味だと思うのですが、bcdadder_4bit.vhdの25~34行目で"x"のインスタンス化の記述を行いました。それなのになぜこのようなエラーが発生するのでしょうか。もし分かりましたら教えていただけると助かります。

###bcdadder_4bit.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bcdadder_4bit is
	port (
		 x , y  : in std_logic_vector(15 downto 0); 
		 z    : out std_logic_vector(19 downto 0);
		 cout : out std_logic );
end bcdadder_4bit;

architecture struct of bcddder_4bit is 
	component bcd_fulladder
		port (
			A, B : in std_logic_vector(3 downto 0);
			ci   : in std_logic;
			co   : out std_logic;
			sum  : out std_logic_vector(3 downto 0));
			
	end component;
	
	signal c : std_logic_vector(3 downto 1); 
	
begin 
	U0 : bcd_fulladder port map (A   => x(3 downto 0), B => y(3 downto 0), ci => '0',
										  sum => z(3 downto 0), co => c(1) );
										  
	U1 : bcd_fulladder port map (A   => x(7 downto 4), B => y(7 downto 4), ci => c(1),
										  sum => z(7 downto 4), co => c(2) );
										  
	U2 : bcd_fulladder port map (A   => x(11 downto 8), B => y(11 downto 8), ci => c(2),
										  sum => z(11 downto 8), co => c(3) );
										  
	U3 : bcd_fulladder port map (A   => x(15 downto 12), B => y(15 downto 12), ci => c(3),
										  sum => z(15 downto 12), co => cout );
										  
end struct;

###bcdfulladder.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity bcd_fulladder is
	port (
		A, B : in std_logic_vector(3 downto 0);
		ci   : in std_logic;
		co   : out std_logic;
		sum  : out std_logic_vector(3 downto 0));
end bcd_fulladder;

  
  
architecture rtl of bcd_fulladder is
	signal tmp, sub : std_logic_vector(4 downto 0);
begin
	tmp <= ("0" & A) + ("0" & B) + ("0000" & ci);
	sub <= tmp - "01010";
	sum <= sub(3 downto 0) when sub(4) = '0' else
	tmp(3 downto 0); 
	co <= not sub(4);
	
end rtl;

###test_bcdfa4bit.vhd

library ieee;
use ieee.std_logic_1164.all;

entity test_bcdfa4bit is
end test_bcdfa4bit;

architecture sim of test_bcdfa4bit is 

component bcdadder_4bit    
		port (
			A, B : in std_logic_vector(15 downto 0);
			ci   : in std_logic;
			c    : out std_logic;
			sum  : out std_logic_vector(19 downto 0) );
	end component;

	signal Ain, Bin : std_logic_vector(15 downto 0);
	signal cin     : std_logic;
	signal cout    : std_logic;
	signal sumout  : std_logic_vector(19 downto 0);
	
begin 

	BCDFA4BIT0 : bcdadder_4bit port map (
		A   => Ain,
		B   => Bin,
		ci  => cin,
		c   => cout,
		sum => sumout);
		
	process
	begin
	
	Ain <= "0000000000000001"; Bin <= "0000000000000011";
	wait for 100 ns;
	
	Ain <= "0000000000000010"; Bin <= "0000000010010001"; 
	wait for 100 ns;
	
	Ain <= "0000000010000100"; Bin <= "0000000000110110"; 
	wait for 100 ns;
	
	Ain <= "0000000101011000"; Bin <= "0000000000110100"; 
	wait for 100 ns;

	Ain <= "0000100100010111"; Bin <= "0000001100110100";	
	wait for 100 ns;

	Ain <= "0101000100010010"; Bin <= "0000001010010001"; 
	wait for 100 ns;

	Ain <= "1000001000011001"; Bin <= "0101011000110100"; 
	wait for 100 ns;
	
	wait;
   end process;
end sim;

configuration cfg_bcdfa4bit of test_bcdfa4bit is
   for sim
   end for;
end cfg_bcdfa4bit;