$ make fpga-images-zybo/boot.binが実行出来ない

Question

前提・実現したいこと

zynq7000を用いてFPGAを動作させたい。
https://github.com/ucb-bar/fpga-zynqの資料の通りに進めています。
Ubuntu16.04の環境で動作を行っています。

$ make fpga-images-zybo/boot.bin

この操作が実行できません。

発生している問題・エラーメッセージ

vivado -mode tcl -source src/tcl/make_bitstream_ZynqMediumFPGAConfig.tcl

****** Vivado v2016.4 (64-bit)
  **** SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017
  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source src/tcl/make_bitstream_ZynqMediumFPGAConfig.tcl
# open_project zybo_rocketchip_ZynqMediumFPGAConfig/zybo_rocketchip_ZynqMediumFPGAConfig.xpr
Scanning sources...
Finished scanning sources
# reset_run synth_1
# reset_run impl_1
# launch_runs synth_1
INFO: [HDL 9-2216] Analyzing Verilog file "/home/ubuntu/box/fpga-zynq/zybo/src/verilog/AsyncResetReg.v" into library work [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/AsyncResetReg.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/ubuntu/box/fpga-zynq/zybo/src/verilog/Top.ZynqMediumFPGAConfig.v" into library work [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/Top.ZynqMediumFPGAConfig.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/ubuntu/box/fpga-zynq/zybo/src/verilog/plusarg_reader.v" into library work [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/plusarg_reader.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/ubuntu/box/fpga-zynq/zybo/src/verilog/rocketchip_wrapper.v" into library work [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/rocketchip_wrapper.v:1]
INFO: [HDL 9-1065] Parsing verilog file "/home/ubuntu/box/fpga-zynq/zybo/src/verilog/clocking.vh" included at line 2. [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/rocketchip_wrapper.v:2]
[Tue Jul 31 15:51:53 2018] Launched synth_1...
Run output will be captured here: /home/ubuntu/box/fpga-zynq/zybo/zybo_rocketchip_ZynqMediumFPGAConfig/zybo_rocketchip_ZynqMediumFPGAConfig.runs/synth_1/runme.log
# wait_on_run synth_1
[Tue Jul 31 15:51:53 2018] Waiting for synth_1 to finish...

*** Running vivado
    with args -log rocketchip_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rocketchip_wrapper.tcl


****** Vivado v2016.4 (64-bit)
  **** SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017
  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source rocketchip_wrapper.tcl -notrace
Command: synth_design -top rocketchip_wrapper -part xc7z010clg400-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 26063 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1119.445 ; gain = 181.086 ; free physical = 10002 ; free virtual = 30342
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'rocketchip_wrapper' [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/rocketchip_wrapper.v:4]
ERROR: [Synth 8-439] module 'system' not found [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/rocketchip_wrapper.v:139]
ERROR: [Synth 8-285] failed synthesizing module 'rocketchip_wrapper' [/home/ubuntu/box/fpga-zynq/zybo/src/verilog/rocketchip_wrapper.v:4]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1160.914 ; gain = 222.555 ; free physical = 9959 ; free virtual = 30299
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
8 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Tue Jul 31 15:52:05 2018...
[Tue Jul 31 15:52:06 2018] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:12 . Memory (MB): peak = 1078.340 ; gain = 0.000 ; free physical = 10279 ; free virtual = 30615
# launch_runs impl_1 -to_step write_bitstream
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.

Vivado% 

ここで動作停止

quit
INFO: [Common 17-206] Exiting Vivado at Tue Jul 31 15:57:44 2018...
ln -sf ../../zybo_rocketchip_ZynqMediumFPGAConfig/zybo_rocketchip_ZynqMediumFPGAConfig.runs/impl_1/rocketchip_wrapper.bit fpga-images-zybo/boot_image/rocketchip_wrapper.bit
cd fpga-images-zybo; bootgen -image boot.bif -w -o boot.bin
[ERROR]  : Can't read BIT file - boot_image/rocketchip_wrapper.bit 
../common/Makefrag:168: ターゲット 'fpga-images-zybo/boot.bin' のレシピで失敗しました
make: *** [fpga-images-zybo/boot.bin] エラー 1

試したこと

当初は下記のようなエラーも出ていたが

awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub

このサイトを参考にエラーメッセージは消すことができた。

https://github.com/pavel-demin/red-pitaya-notes/issues/426