質問編集履歴
1
情報の追加
test
CHANGED
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@@ -1 +1 @@
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1
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-
【Vivado】エラーの意味を教えてほしい
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1
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bu【Vivado】エラーの意味を教えてほしい
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test
CHANGED
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@@ -153,3 +153,79 @@
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153
153
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[get_ports { LED_RGB[0] }]; # Blue
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```
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156
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+
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158
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159
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##表示されたログ
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160
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161
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```
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162
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163
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Report BlackBoxes:
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164
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+
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165
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+-+--------------+----------+
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166
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+
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167
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| |BlackBox name |Instances |
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168
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+
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169
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+-+--------------+----------+
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170
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+
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171
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+-+--------------+----------+
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175
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Report Cell Usage:
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177
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+------+-----+------+
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179
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| |Cell |Count |
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180
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+
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181
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+------+-----+------+
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182
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183
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|1 |OBUF | 3|
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184
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+
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185
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+------+-----+------+
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186
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187
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---------------------------------------------------------------------------------
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188
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189
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1118.707 ; gain = 0.000
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190
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+
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191
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+
---------------------------------------------------------------------------------
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192
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+
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193
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Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
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194
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+
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195
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+
Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1118.707 ; gain = 0.000
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196
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+
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197
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+
Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1118.707 ; gain = 0.000
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198
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+
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199
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+
INFO: [Project 1-571] Translating synthesized netlist
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200
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201
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.707 ; gain = 0.000
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202
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+
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203
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+
INFO: [Project 1-570] Preparing netlist for logic optimization
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204
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+
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205
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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206
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+
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207
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+
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.707 ; gain = 0.000
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208
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+
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209
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+
INFO: [Project 1-111] Unisim Transformation Summary:
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210
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+
|
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211
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+
No Unisim elements were transformed.
|
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212
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+
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213
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+
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214
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+
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215
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+
Synth Design complete, checksum: 94b5bcf5
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216
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+
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217
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+
INFO: [Common 17-83] Releasing license: Synthesis
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218
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+
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219
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+
15 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
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220
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+
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221
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+
synth_design completed successfully
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|
222
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+
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223
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synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1118.707 ; gain = 0.000
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224
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+
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225
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INFO: [Common 17-1381] The checkpoint 'C:/Xilinx/FPGA/Zybo_Z7-10/blink/blink.runs/synth_1/blink.dcp' has been generated.
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226
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+
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227
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INFO: [runtcl-4] Executing : report_utilization -file blink_utilization_synth.rpt -pb blink_utilization_synth.pb
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228
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+
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229
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INFO: [Common 17-206] Exiting Vivado at Mon Aug 2 05:11:25 2021...
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230
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+
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|
231
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+
```
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