##問題
XilinxのVivadoでコンパイルをしたところ以下のようなエラー画面が表示されました。
このエラーはどういった意味なのでしょうか。どうしたら解決しますか?
一応コンパイルは[PROGRAM AND DEBUG]→[Generate Bitstream]の手順で行いました。
##コンパイルしたいファイルの中身①(vファイル)
module blink ( input CLK, input RST, output reg[2:0] LED_RGB ); reg [25:0] cnt26; always @(posedge CLK ) begin if ( RST ) cnt26 <= 26'h0; else cnt26 <= cnt26 + 1'h1; end wire ledcnten = (cnt26==26'h3ffffff); reg [2:0] cnt3; always @(posedge CLK ) begin if ( RST ) cnt3 <= 3'h0; else if ( ledcnten ) if (cnt3==3'd4) cnt3 <=3'h0; else cnt3 <= cnt3 + 3'h1; end always @* begin case ( cnt3 ) 3'd0: LED_RGB = 3'b100; 3'd0: LED_RGB = 3'b010; 3'd0: LED_RGB = 3'b001; 3'd0: LED_RGB = 3'b111; 3'd0: LED_RGB = 3'b000; default:LED_RGB = 3'b100; endcase end endmodule
##コンパイルしたいファイルの中身②(xdcファイル)
## Zybo Z7 constraints file ## chapter: 2 ## project: blink #Clock signal set_property PACKAGE_PIN K17 [get_ports { CLK }] set_property IOSTANDARD LVCMOS33 [get_ports { CLK }] create_clock -add -name sys_clk_pin -period 8.00 \ -waveform {0 4} [get_ports { CLK }] #Reset set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } \ [get_ports { RST }]; # BTN[3] #RGB LED set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } \ [get_ports { LED_RGB[2] }]; # Red set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } \ [get_ports { LED_RGB[1] }]; # Green set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } \ [get_ports { LED_RGB[0] }]; # Blue
##表示されたログ
Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |OBUF | 3| +------+-----+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1118.707 ; gain = 0.000 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1118.707 ; gain = 0.000 Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1118.707 ; gain = 0.000 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.707 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.707 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete, checksum: 94b5bcf5 INFO: [Common 17-83] Releasing license: Synthesis 15 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1118.707 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Xilinx/FPGA/Zybo_Z7-10/blink/blink.runs/synth_1/blink.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file blink_utilization_synth.rpt -pb blink_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Mon Aug 2 05:11:25 2021...
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